
// Library name: Variation
// Cell name: inverter
// View name: schematic
subckt inverter in out vdd vss
    M0 (out in vss vss) NMOS_VTL w=wn_inverter l=ln_inverter as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (out in vdd vdd) PMOS_VTL w=wp_inverter l=lp_inverter as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends inverter
// End of subcircuit definition.

// Library name: HW4
// Cell name: Latch
// View name: schematic
subckt Latch clk d q vdd vss
    M12 (net10 net17 vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M13 (q net10 vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M10 (q net22 net17 vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (d clk net17 vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M0 (net22 clk vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M11 (net10 net17 vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M14 (q net10 vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M7 (q clk net17 vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M6 (d net22 net17 vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M5 (net22 clk vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends Latch
// End of subcircuit definition.

// Library name: Variation
// Cell name: flip_flop
// View name: schematic
subckt flip_flop clk d q vdd vss
    I3 (clk net14 q vdd vss) Latch
    I2 (net6 d net14 vdd vss) Latch
    M0 (net6 clk vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (net6 clk vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends flip_flop
// End of subcircuit definition.

// Library name: Variation
// Cell name: mux
// View name: schematic
subckt mux a b control out vdd vss
    M17 (net051 net066 vdd vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M7 (a control net066 vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M19 (out net051 vdd vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (b net59 net066 vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M0 (net59 control vdd vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M16 (net051 net066 vss vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M6 (b control net066 vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M5 (net59 control vss vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M18 (out net051 vss vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M10 (a net59 net066 vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends mux
// End of subcircuit definition.

// Library name: Variation1
// Cell name: test_circuit_17
// View name: schematic
I40 (net0106 freq1 net42 net123) inverter
I39 (net0110 net0106 net42 net123) inverter
I37 (net0114 net0110 net42 net123) inverter
I35 (net0118 net0114 net42 net123) inverter
I33 (net0122 net0118 net42 net123) inverter
I31 (net0126 net0122 net42 net123) inverter
I10 (net15 net0126 net42 net123) inverter
I9 (net19 net15 net42 net123) inverter
I8 (net23 net19 net42 net123) inverter
I7 (net27 net23 net42 net123) inverter
I6 (net31 net27 net42 net123) inverter
I5 (net35 net31 net42 net123) inverter
I4 (net39 net35 net42 net123) inverter
I3 (net43 net39 net42 net123) inverter
I2 (net47 net43 net42 net123) inverter
I1 (net51 net47 net42 net123) inverter
I0 (freq1 net51 net42 net123) inverter
I41 (net111 net0201 net0171 vdd gnd) flip_flop
I38 (net111 net0181 scan_out vdd gnd) flip_flop
I36 (net111 net0186 net0181 vdd gnd) flip_flop
I34 (net111 net0191 net0186 vdd gnd) flip_flop
I32 (net111 net0196 net0191 vdd gnd) flip_flop
I30 (net111 net0171 net0196 vdd gnd) flip_flop
I21 (net111 net61 net0201 vdd gnd) flip_flop
I20 (net111 net66 net61 vdd gnd) flip_flop
I19 (net111 net71 net66 vdd gnd) flip_flop
I18 (net111 net76 net71 vdd gnd) flip_flop
I17 (net111 net81 net76 vdd gnd) flip_flop
I16 (net111 net86 net81 vdd gnd) flip_flop
I15 (net111 net91 net86 vdd gnd) flip_flop
I14 (net111 net96 net91 vdd gnd) flip_flop
I13 (net111 net101 net96 vdd gnd) flip_flop
I12 (net111 net106 net101 vdd gnd) flip_flop
I11 (net111 net117 net106 vdd gnd) flip_flop
I23 (clk scan_clk scan_en net111 vdd gnd) mux
I22 (scan_out scan_in scan_en net117 vdd gnd) mux
M33 (gnd scan_out net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M32 (net42 scan_out vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M31 (gnd net0181 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M30 (net42 net0181 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M29 (gnd net0186 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M28 (net42 net0186 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M27 (gnd net0191 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M26 (net42 net0191 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M25 (gnd net0196 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M24 (net42 net0196 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M23 (gnd net0171 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M22 (net42 net0171 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M21 (gnd net0201 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M20 (gnd net61 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M19 (gnd net66 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M18 (gnd net71 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M17 (gnd net76 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M16 (gnd net81 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M15 (gnd net86 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M14 (gnd net91 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M13 (gnd net96 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M12 (gnd net101 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M11 (gnd net106 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M10 (net42 net0201 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M9 (net42 net61 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M8 (net42 net66 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M7 (net42 net71 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M6 (net42 net76 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M5 (net42 net81 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M4 (net42 net86 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M3 (net42 net91 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M2 (net42 net96 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M1 (net42 net101 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M0 (net42 net106 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
C0 (net123 gnd) capacitor c=1p
C1 (net42 gnd) capacitor c=1p
